Memories are an integral part of a system on chip (SoC). Different types of memories are preferred based on the application and their intended use. First-in first-out (FIFO) memories are commonly used in memory-dominated architecture of SoC devices. Unlike other memories, FIFO memories have no address buses to retrieve data from a particular address. These memories have separate read and write address counters, which increment themselves on each read and write operation, respectively. These counters reset themselves to the first address on reaching the last address in the FIFO memory. FIFO memories occupy less space in comparison to conventional memories due to a lack of address generation devices and address buses. They are extensively used in devices where data retrieval is required in a fixed order.
FIFO memory chips are used in buffering applications between devices that operate at different speeds, or in applications where data must be stored temporarily for further processing. Typically, this type of buffering is used to increase bandwidth and to prevent data loss during high-speed communications. As the term FIFO implies, data is released from the buffer in the order of its arrival. Some FIFO memories read with one clock and write with another simultaneously. Synchronous operations require a clock, but asynchronous operations do not. Flow control generates full and empty signals so that inputs do not overwrite the contents of the buffer. Depending on the device, a FIFO memory can be unidirectional or bidirectional. A FIFO memory can also include parallel inputs and outputs as well as programmable flags.
A FIFO memory is commonly used for storage of code for programmable devices that execute a set of operations on multiple blocks/locations. For instance, a programmable built-in self test (BIST) executes a sequence of operations on all memory locations. By maintaining the code sequence of memory operations in a FIFO memory, the BIST reads the FIFO memory for the code and executes the operations. If the number of operations is equal to the length of the FIFO, then the BIST does not reset the FIFO memory after all the operations have been executed on one location as the FIFO memory resets its address counter to the first location. But if the FIFO length is not equal to the number of operations, the BIST keeps track of the number of operations executed and resets the FIFO address counter accordingly. This leads to a significant hardware overhead for control circuitry in the BIST, and also slows down the BIST speed.
Additionally, after the execution of the last operation on a location, the BIST needs the first operation to execute on the next location in the next clock cycle. This means that the FIFO counters are reset before the next clock cycle. A designer has to adapt his synchronous design on negative edges as well, which is generally undesirable and is not supported by many design tools.
The prior art architecture is illustrated in FIG. 1. Each data source (Block 1 and Block 3) and their associated data receiver (Block 2 and Block 4) has a dedicated FIFO memory (FIFO 1 and FIFO 2) regardless of the FIFO length and the operation mode. This leads to an existence of redundant FIFO memories, and consequently, to a waste of silicon area.
U.S. Pat. No. 6,651,201 discloses an example architecture with a fixed length FIFO memory. This patent describes a BIST wherein the BIST controller has a dedicated built-in micro-code storage device (i.e., a FIFO). The micro-code storage device is the largest contributor to area overhead due to the presence of the BIST on the chip. A variable length FIFO, which may be shared between several blocks, is highly desirable in such instances to reduce the silicon area.
It is desirable to have a particular length FIFO memory in BISTs and in many other blocks on a SoC. Dedicated FIFO memories of different lengths are used for different blocks on a chip resulting in extra silicon area overhead. One approach is to share the FIFO memories between blocks that require equal length FIFO memories. However, this sharing may not be possible where parallel execution is required for the FIFO memory sharing the blocks. In addition to area overhead, the presence of multiple FIFO memories significantly slows down the design process. Time taken in the design process from generating the FIFO code to layout of the chip is several weeks. If the FIFO memory has to be varied for a different code, the design process has to be repeated, resulting in an unnecessary slowdown of the design process.
There is a need for an improved FIFO memory that will reduce the number of FIFO memories required on a chip. Moreover, there is a need for a FIFO memory that may not require significant control circuitry to perform the FIFO counter resetting. Additionally, there is a need to address the negative edge clock problem mentioned above and to reduce the design cycle time.